The present invention relates generally to semiconductor devices, and more particularly to metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) devices.
In the manufacture of semiconductor devices conductive polycide is often employed to impart enhanced conductivity to conductive layers. Polycide is a combination of polysilicon and refractory metal suicide layers that offers lower resistivity than polysilicon alone. Polycides may be formed using silicides of a variety of refractory metals including, but not limited to, metals such as titanium, tungsten, tantalum, molybdenum, etc. In one common example, the silicidation of polysilicon (e.g., to form polycide) has been previously implemented to reduce the electrical resistance of gate electrode and interconnect metallization in metal-oxide-semiconductor field effect transistor (xe2x80x9cMOSFETxe2x80x9d) devices.
Polycides may be formed in a number of different ways including, for example, by depositing a refractory metal onto a polysilicon layer, followed by annealing at a sufficiently high temperature to form a metal silicide. Alternatively, metal silicide may be deposited, for example, by using sputtering, low pressure chemical vapor deposition (xe2x80x9cLPCVDxe2x80x9d), evaporation, etc. In one example of the latter method, U.S. Pat. No. 5,946,599 describes LPCVD deposition of tungsten silicide onto doped-polysilicon.
Although various methods and improvements thereto have been developed for the fabrication of conductive polycide, problems in the fabrication of polycides still exist. For example, one major problem commonly experienced with existing polycide fabrication technologies is lack of adhesion between the metal silicide layer and the polysilicon layer. This lack of adhesion, or adhesion loss, may result in separation or peeling of a refractory metal silicide layer from an underlying polysilicon layer, translating to lowered product yield.
Attempts have been made to address adhesion problems encountered with polycide layers, such as those encountered during fabrication of MOSFET devices. For example, U.S. Pat. No. 5,089,432 describes encapsulation of a polycide layer with a tetraethoxysilane (xe2x80x9cTEOSxe2x80x9d) deposited silicon dioxide dielectric layer which is preserved above the polycide layer via masking during spacer etch to improve adhesion. In another example, U.S. Pat. No. 5,946,566 proposes improving adhesion between metal silicide and polysilicon layers by deposition of a polysilicon layer having a wavy or undulated surface, i.e., hemi-spherical grain (xe2x80x9cHSGxe2x80x9d) polysilicon or acid-treated polysilicon. Drawbacks associated with such methods include increased cost and process complexity. Further, encapsulation of polycide requires very tight control of spacer densification conditions, e.g., to maintain a very controlled oxidation environment in a furnace tube, in order to maintain the integrity of the encapsulation.
Disclosed herein is a non-oxidizing spacer densification method for producing semiconductor devices including, but not limited to, MOSFET devices such as fully integrated complementary metal-oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) devices having non-volatile memory. Advantageously, the disclosed method may be implemented during semiconductor fabrication to provide low cost and robust processes for polycide formation with little or substantially no adhesion loss experienced during spacer oxide densification steps. The disclosed method also makes possible good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments. The disclosed method further simplifies the spacer oxide densification step and process sequence since no thermal oxide is grown over the non-volatile memory stack structure, non-memory control gate stack structure and source/drain regions during spacer densification, eliminating the need to manage thermal oxide growth during this step. Further, the disclosed non-oxidizing method may be used to achieve MOSFET spacer oxide densification while at the same time minimizing or substantially preventing off-site oxide growth loss due to oxidation of exposed silicon surfaces during the densification step.
By employing non-oxidizing species in a MOSFET spacer densification step, the disclosed method surprisingly eliminates the need for the added complexity of a metal silicide top encapsulation layer and the need for controlled oxidation conditions during spacer densification employed in the practice of conventional MOSFET fabrication methods without detrimental effects on the performance of MOSFET transistors. This method of fabrication is contrary to accepted MOSFET spacer densification methodology that employs oxidizing species to grow a thin layer of silicon dioxide in the source and drain areas during spacer densification before, for example, deposition of polysilicon metal dielectric layers.
Thus, in one embodiment, the disclosed method may be practiced to minimize or substantially eliminate undesirable growth of oxidation products (e.g., WxSiyOz on tungsten-based polycide layers) that are believed to result in polycide adhesion loss, and implementation of MOSFET spacer densification in a non-oxidizing environment eliminates the need for encapsulation methods to prevent polycide adhesion loss. Further, the disclosed method makes the spacer etch step substantially completely tolerant or independent of micro-loading effects, i.e., differences in amount of anti-reflective layer that is removed from the top of the polycide layer during spacer etch steps. In this regard, the disclosed method may be successfully practiced under conditions ranging from substantially no removal of anti-reflective layer during spacer oxide etch to almost complete removal of anti-reflective layer during spacer oxide etch (e.g., only a few mono-layers of anti-reflective layer remaining). This characteristic advantageously reduces expense and complexity of the spacer oxide etch step.
Advantageously, the disclosed method may be further implemented in a low cost manner to fabricate high yield and high reliability polycide layers in an existing MOSFET fabrication unit. In this regard, the disclosed method may be implemented in a manner that reduces necessary capital investment by using existing physical vapor deposition (xe2x80x9cPVDxe2x80x9d) equipment for the sputter deposition of metal silicide, e.g., by addition of a sputter chamber to existing PVD equipment. Additional cost savings may be realized by using rapid thermal processing (xe2x80x9cRTPxe2x80x9d) methodology, e.g., low DT (e.g. time at temperature), rather than slow controlled furnace tube oxidizing anneal methodologies that are employed in conventional spacer densification methods. Further cost advantages may be realized using the disclosed method by employing plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) for anti-reflective layer (xe2x80x9cARLxe2x80x9d) deposition rather than using the costlier spin-on deposition of ARL.
In one respect then, disclosed herein is a method of densifying a spacer oxide that at least partially surrounds a polycide structure. The method includes densifying the spacer oxide in a non-oxidizing ambient.
In another respect, disclosed herein is a method of forming a semiconductor structure on a substrate. The method may include forming a polycide structure having at least one polysilicon layer and at least one metal silicide layer, forming a spacer oxide on the polycide structure to at least partially surround the polycide structure, and densifying the spacer oxide in a non-oxidizing ambient to form the semiconductor structure.
In another respect, disclosed herein is a method of forming a non-volatile memory stack structure and a non-memory control gate stack structure of an integrated semiconductor device on a silicon substrate. The method may include forming a dielectric isolation region on the silicon substrate between an active non-volatile memory mesa area and an active non-memory mesa area of the silicon substrate, forming a memory cell oxide layer on the silicon substrate over the active non-volatile memory mesa area, forming a doped floating gate polysilicon layer on the memory cell oxide layer over the active non-volatile memory mesa area, forming an inter-poly oxide layer on the doped floating gate polysilicon layer over the active non-volatile memory mesa area, forming a thin gate oxide layer on the silicon substrate over the active non-memory mesa area, forming a doped control gate polysilicon layer on the thin gate oxide of the active non-memory mesa area and on the inter-poly oxide layer of the active non-volatile memory mesa area, forming a refractory metal silicide layer on the doped control gate polysilicon layer over the active non-volatile memory mesa area so as to form said non-volatile memory stack structure over the active non-volatile memory mesa area, and forming heavily doped non-volatile memory source/drain regions of the non-volatile memory stack structure in the silicon substrate over the active non-volatile memory mesa area. The method may also include forming a refractory metal silicide layer on the doped control gate polysilicon layer over the active non-memory mesa area so as to form said non-memory control gate stack structure over the active non-memory mesa area, and forming lightly doped non-memory source/drain regions of the non-memory control gate stack structure in the silicon substrate over the active non-memory mesa area. The method may further include forming a spacer oxide side layer on each of the non-volatile memory stack and the non-memory control gate stack structures, densifying the spacer oxide side layers in a non-oxidizing ambient; and forming heavily doped non-memory source/drain regions of the non-memory control gate stack structure in the silicon substrate over the lightly doped non-memory source/drain regions.
In another respect, disclosed herein is a relatively low cost and high yielding method for the integration of tungsten polycide deposition into an existing CMOS fabrication facility. In one embodiment, the method may combine the physical vapor deposition (xe2x80x9cPVDxe2x80x9d) or sputter deposition of a tungsten polycide layer, plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d) of a silicon oxynitride anti-reflective layer (xe2x80x9cARLxe2x80x9d), and rapid thermal processor spacer densification in the presence of a non-oxidizing species (e.g., nitrogen) to produce a non-encapsulated polycide layer having good adhesion characteristics. In this embodiment, RTP in a non-oxidizing nitrogen environment advantageously may be employed to achieve spacer densification without the need for encapsulation methods to prevent polycide adhesion loss.
In another respect, disclosed is a method of fabricating a tungsten polycide interconnection layer in a fully integrated CMOS device having embedded analog sections and non-volatile memory sections. In one exemplary embodiment, the method may include first depositing a layer of amorphous silicon by, for example, low pressure chemical vapor deposition (xe2x80x9cLPCVDxe2x80x9d), subsequently doping the deposited layer by, for example, ion implantation, followed by annealing the deposited and doped layer using, for example, RTP to activate the dopant and to reduce damage. The method may next include depositing a tungsten silicide layer on the doped amorphous silicon by, for example, using PVD followed by RTP of the tungsten silicide layer in a nitrogen environment to form a tungsten-based polycide structure. The method may next include depositing a silicon-rich oxynitride layer onto the tungsten-based polycide structure to serve as a polycide ARL for the patterning process using, for example, PECVD deposition. Non-volatile memory and control gate polycide stack structures may next be fabricated, for example, by patterning the tungsten-based polycide structure using photolithography followed by reactive ion etch (xe2x80x9cRIExe2x80x9d) processes, and a thin oxide may be subsequently grown on the sidewalls of non-volatile memory and control gate polycide stacks, for example, within a furnace tube. Source and drain areas may next be n-doped and/or p-doped to provide desired functionality. The method may next include depositing an oxide spacer layer using, for example, PECVD tetraethyl orthosilicate (xe2x80x9cTEOSxe2x80x9d) deposition. The spacer layer may next be removed and over-etched from the top of the polycide and from the source and drain areas using, for example, RIE. Densification of the spacer and tungsten-based polycide structure may then be accomplished using RTP and a non-oxidizing environment in order to prevent polycide oxidation induced peeling.